| My Home Page | Background | Research | Publications | Contact	Rakesh Kumar Assistant Professor Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaign 1308 West Main Street Urbana, IL 61801 USA. Research: I like to study and build processors and systems with focus on a) scalability: ability to seamlessly exploit multiple levels of concurrency in workloads, b) adaptability: proactive adjustment to the intrinsic workload type and application requirements, and c) programmability: cooperative information exchange between hardware and software for productivity and efficiency. Specifically, my research interests include multi-core and multithreaded architectures, low-power and complexity-effective architectures, on-chip interconnects, compilation and OS issues for multithreaded architectures, embedded and reconfigurable architectures, etc. Current research goal is to build a truly adaptable processor that can adapt to all workload conditions and characteristics, and can therefore deliver performance and power characteristics as if it were designed for close to the best case, on average, instead of the average case, at best. We call this initive Amoebic Computing. Another research goal is to investigate how to build and use many-core (possibly hundreds of cores) processors. This involves studying both bottlenecks like interconnection and coherence, worst-case power, etc., as well as opportunities like enhancing reliability, availability, usability, etc. I am also interested in revisiting the roles of hardware and software in the computing stack, with special focus on mechanisms vs policies and what goes where (e.g., should process management and scheduling be done in hardware?). I also have very broad potential interests. Please feel encouraged to take a shot at convincing me to work on something different that you are excited about. Email Address: rakeshk AT uiuc.edu *************************WEB BOARD******************************** I am looking for motivated graduate/undergraduate students. If you are a UIUC graduate/undergraduate student looking for an advisor or if you are someone interested in applying to UIUC for graduate studies, email me if you want to do research in computer architecture, reconfigurable computing, or hardware/software interface. See my research/publications pages for a sampling of my research. Please attach your CV as well. Our research on hardware support for economic models for many-cores just got featured in HPCWire. A locally cached copy can be found here. There was also followup coverage on News Gazette, Slashdot, ACM News, etc. Our DATE-2008 paper on "Magellan: A Framework for Fast Muti-core Design Space Exploration and Optimization Using Search and Machine Learning " is now online. A longer version appears as UIUC CRHC Technical Report CRHC-07-05, October 2007 (PDF). . Our dasCMP-2007 paper on "Servo: A Programming Model for Many-core Computing" is now online. A recent press article on our research. A locally cached copy can be found here. Organizing the Workshop on Design, Architecture, and Simulation of Chip Multiprocessors (dasCMP) again this year. Please submit good papers. Serving on ISPASS-2008 and INTERACT-12 program committees. Please submit good papers. Served on the recent MICRO-40 program committee and the ISCA-2007 organizing committee. Running the CSL computer engineering seminar series. Please attend.