|  Home | Call for Papers | Workshop Program | Paper Submission | Organizing Committee | Important Dates | dasCMP 2007 | Contact				Call for Papers Workshop on Design, Architecture, and Simulation of Chip Multi-Processors dasCMP 2008 http://passat.crhc.uiuc.edu/dasCMP Held in conjunction with the 41^st Annual International Symposium on Microarchitecture Sunday, November 9, 2008, Lake Como Italy Organizers Norman P. Jouppi, HP Labs (norm.jouppi@hp.com) Rakesh Kumar, UIUC (rakeshk@uiuc.edu) Dean M. Tullsen, UC San Diego (tullsen@cs.ucsd.edu) Goal of the Workshop Chip multiprocessor architectures are becoming increasingly attractive as an option to provide high instruction throughput while keeping power and complexity under control. Such architectures have also been shown to have scalability and productivity advantages. Multi-core processors are fast becoming mainstream. However, putting multiple cores on a die throws open several interesting research and design issues. From choosing the number of cores on the die to choosing the complexity of these cores, from constructing a chip multiprocessor out of off-the-shelf cores to creating a customized ``multi-core aware'' multi-core design, there are several difficult questions that need to be addressed. Connecting the cores, determining the right memory subsystem, ensuring coherence and consistency of data, and trying to limit the area and power budgets, all require a deep understanding of issues and innovative application of ideas. Even simulating and evaluating a chip multiprocessor represents a significant challenge. There are equally interesting issues regarding programming and compilation for chip multiprocessors. All these questions and issues become more difficult and complicated for architectures with more than two cores. The goal of this workshop is to bring together researchers, computer architects, and engineers working on a broad spectrum of topics pertaining to the architecture, simulation, and design of chip multiprocessors. The workshop will provide a forum for presenting and exchanging new ideas and experiences in this area and to discuss and explore hardware/software techniques and tools for efficient multi-core computation. Contributions from all aspects of multi-core architecture, design and simulation are encouraged; related areas like application of CMPs to solve new problems and programming and compilation for CMP architectures are welcome as well. Topics of Interest The topics of interest for the workshop will include but are not limited to: Core design for CMPs, e.g. helper cores, conjoined-cores, heterogeneous multi-core architectures, etc. Novel Microarchitectures, e.g. tiled architectures, master-slave architectures, etc. Interconnects in CMPs, e.g. connections between cores, connections between cores and on-chip memory, networks-on-chip, etc. Cache coherence and consistency for CMPs On-chip/off-chip memory hierarchy and design for CMPs Applications of CMP architectures for solving problems, e.g. using multiple cores to enhance security, reliability, improve single-thread performance, reduce power, etc. Speculative Multithreading for CMPs Compiler, scheduling, and OS support for CMPs Programmability enhancements for CMPs Simulation and evaluation of CMPs, e.g. new simulators, simulation techniques, analytical evaluations Efficient design space exploration for multi-core architectures Workload/benchmark design and analysis for multi-core processors Performance evaluation/analysis/design of real multi-core processors Full length conference papers are fine but not a requirement. Out-of-the box idea/position papers specially encouraged. Submission instructions can be found here. Program Committee Krste Asanovic, Berkeley Rajeev Balasubramonian, Utah Norman P. Jouppi, HP Manolis Katenvis, FORTH and U. Crete, Greece Stefanos Kaxiras, U. Patras, Greece Christos Kozyrakis, Stanford Rakesh Kumar, UIUC Jim Laudon, Sun Sally McKee, Cornell Martha Mercaldi, Columbia Chuck Moore, AMD Ravi Nair, IBM Ronny Ronen, Intel Per Stenstrom, Chalmers Dean Tullsen, UCSD David Wood, Wisconsin Schedule Submission Deadline: August 15, 2008 (one week extension upon request) Acceptance Notification: October 4, 2008 Final Version due: October 26, 2008
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